library IEEE; use IEEE.std_logic_1164.all; entity freddie is port ( clk_in :in std_logic; clk_out :out std_logic; rst :in std_logic; extsel :in std_logic; casinh :in std_logic; phi2 :in std_logic; rw :in std_logic; a :in std_logic_vector(15 downto 0); osc :out std_logic; ras :out std_logic; cas :out std_logic; w :out std_logic; ba :out std_logic_vector(7 downto 0) ); end freddie; architecture a_freddie of freddie is signal neg_clk :std_logic; signal fcount :std_logic_vector(2 downto 0); signal mpy :std_logic; signal l_rw :std_logic; begin freddie_counter: process(clk_in,rst) begin if rst='0' then fcount <= "000"; elsif clk_in'event and clk_in='1' then fcount(0) <= (not fcount(2) and not fcount(1) and not phi2) or (fcount(2) and fcount(1) and phi2); fcount(1) <= (not fcount(2) and fcount(0) and not phi2) or (not fcount(2) and fcount(1) and not fcount(0) and not phi2) or (fcount(2) and fcount(1) and not fcount(0) and phi2); fcount(2) <= (not fcount(2) and fcount(1) and not fcount(0) and not phi2) or (fcount(2) and fcount(1) and not fcount(0) and phi2) or (fcount(2) and fcount(0) and phi2); end if; end process freddie_counter; ras_rw: process(neg_clk,rst) begin if rst='0' then ras <= '1'; l_rw <= '1'; elsif neg_clk'event and neg_clk='1' then if fcount="000" or fcount="001" or fcount="011" then ras <= '1'; else ras <= '0'; end if; if fcount="010" then l_rw <= rw; end if; end if; end process ras_rw; neg_clk <= not clk_in; clk_out <= neg_clk; osc <= '1' when fcount(2 downto 1)="00" or fcount(2 downto 1)="11" else '0'; mpy <= '0' when fcount="001" or fcount="011" or fcount="010" else '1'; ba(0) <= a(0) when mpy='0' else a(8); ba(1) <= a(1) when mpy='0' else a(9); ba(2) <= a(2) when mpy='0' else a(10); ba(3) <= a(3) when mpy='0' else a(11); ba(4) <= a(4) when mpy='0' else a(12); ba(5) <= a(5) when mpy='0' else a(13); ba(6) <= a(6) when mpy='0' else a(14); ba(7) <= a(7) when mpy='0' else a(15); w <= rw when fcount="001" or fcount="011" or (fcount="010" and neg_clk='0') else l_rw; cas <= '1' when extsel='0' or casinh='0' or fcount="011" or fcount="010" or fcount="110" or (l_rw='1' and fcount="001") or (l_rw='0' and fcount="111") or (l_rw='0' and fcount="001" and neg_clk='1') or (l_rw='0' and fcount="101" and neg_clk='0') else '0'; end a_freddie;