library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity tb_freddie is
end tb_freddie;

architecture tb_freddie_a of tb_freddie is

component freddie is
port (
		clk_in  :in std_logic;
		clk_out :out std_logic;
		rst		:in std_logic;
		extsel  :in std_logic;
		casinh  :in std_logic;
		phi2    :in std_logic;
		rw      :in std_logic;
		a       :in std_logic_vector(15 downto 0);
		osc     :out std_logic;
		ras     :out std_logic;
		cas     :out std_logic;
		w       :out std_logic;
		ba      :out std_logic_vector(7 downto 0)
);
end component freddie;

signal s_clk_in  :std_logic;
signal s_clk_out :std_logic;
signal s_rst	 :std_logic;
signal s_extsel  :std_logic;
signal s_casinh  :std_logic;
signal s_phi2    :std_logic;
signal s_rw      :std_logic;
signal s_a       :std_logic_vector(15 downto 0);
signal s_osc     :std_logic;
signal s_ras     :std_logic;
signal s_cas     :std_logic;
signal s_w       :std_logic;
signal s_ba      :std_logic_vector(7 downto 0);
constant period	 :time:=35ns;

begin

connect: freddie port map(s_clk_in, s_clk_out, s_rst,  s_extsel, s_casinh, s_phi2, s_rw, s_a, s_osc, s_ras, s_cas, s_w, s_ba);

clock_14MHz: process
	begin
		s_clk_in <= '1';
		wait for period;
		s_clk_in <= '0';
		wait for period;
	end process clock_14MHz;

clock_o2: process
    begin
		s_phi2 <= '0';
		wait for period*7;
		s_phi2 <= '1';
		wait for period*8;
		s_phi2 <= '0';
		wait for period;
	end process clock_o2;

main: process
	begin

	s_rst <= '0';
	s_rw <= '0';
	s_extsel <= '0';
	s_casinh <= '0';
	s_a <= "0000000011111111";
	wait for period*11;

	s_rst <='1';
	wait for period*5;

	s_extsel <= '1';
	s_casinh <= '1';
	wait for period*16;

	s_rw <= '1';
	wait for period*16;

	s_rw <= '0';
	wait for period*32;

	assert false severity failure;
	
	end process main;
	
end tb_freddie_a;